Multiple Single Input Change Vectors for Built-In Self Test (MSIC-BIST)

Low Power MSIC Signatures for Effective BIST Design

In BIST architecture the ATPG is the one of important consideration .the performance also the depends on the appropriate ATPG generation .in our paper we propose the novel method of multiple single input change (MSIC) test patterns that are intended for the scan chain. In order to develop any method we need to consider the area and power aspects for the advanced VLSI designs, and also able to p...

Efficient Test Pattern Generator for BIST using Multiple Single Input Change Vectors

On Reducing Aliasing Effects and Improving Diagnosis of Logic BIST Failures

Diagnosing failing vectors in a Built-In Self Test (BIST) environment is a difficult task because of the highly compressed signature coming out of the Multiple Input Shift Register (MISR). The root cause of the failure must be initially narrowed down to the failing vectors and also the scan cells at which mismatches occurred. In this work, we propose a method for accurately determining the firs...

An Adaptive BIST to Detect Multiple Stuck-Open Faults in CMOS circuits

Design of an adaptive built-in-self-test (BIST) scheme for detecting multiple stuck-open faults in a CMOS complex cell is proposed. The test pattern generator (TPG) adaptively generates a subset of singleinput-change (SIC) test pairs based on the past responses of the circuit under test (CUT). The design is universal, i.e., independent of the structure and functionality of the CUT. The average ...

RSIC Generation: A Solution for Logic BIST

High defect coverage requires good coverage of different fault types. In this paper, we present a comprehensive test vector generation technique for BIST, called Random Single Input Change (RSIC) generation, that can be used to generate tests for many arbitrary misbehaviors that can occur in digital systems, thus providing a single on-chip test generation solution. By proving the effectiveness ...